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| 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY FLASH MEMORY MT28F322D20 MT28F322D18 Low Voltage, Extended Temperature 0.18m Process Technology FEATURES * Flexible dual-bank architecture - Support for true concurrent operation with zero latency - Read bank a during program bank b and vice versa - Read bank a during erase bank b and vice versa * Basic configuration: Seventy-one erasable blocks - Bank a (8Mb for data storage) - Bank b (24Mb for program storage) * VCC, VCCQ, VPP voltages - 1.70V (MIN), 1.90V (MAX) VCC, VCCQ (MT28F322D18 only) - 1.80V VCC, VCCQ (MIN); 2.20V VCC (MAX)and 2.25V VCCQ (MAX) (MT28F322D20 only) - 0.9V (TYP) VPP (in-system PROGRAM/ERASE) - 12V 5% (HV) VPP tolerant (factory programming compatibility) * Random access time: 70ns/80ns @ 1.70V VCC * Burst Mode read access (MT28F322D20) - MAX clock rate: 54 MHz (tCLK = 18.5ns) - Burst latency: 70ns @ 1.80V VCC and 54 MHz - tACLK: 17ns @ 1.80V VCC and 54 MHz * Page Mode read access1 - Eight-word page - Interpage read access: 70ns/80ns @ 1.80V - Intrapage read access: 30ns @ 1.80V * Low power consumption (VCC = 2.20V) - Asynchronous READ < 15mA (MAX) - Standby < 50A - Automatic power saving feature (APS) * Enhanced write and erase suspend options - ERASE-SUSPEND-to-READ within same bank - PROGRAM-SUSPEND-to-READ within same bank - ERASE-SUSPEND-to-PROGRAM within same bank * Dual 64-bit chip protection registers for security purposes * Cross-compatible command support - Extended command set - Common flash interface * PROGRAM/ERASE cycle - 100,000 WRITE/ERASE cycles per block NOTE: 1. Data based on MT28F322D20 device. 2. A "5" in the part mark represents two different frequencies: 54 MHz (MT28F322D20) or 52 MHz (MT28F322D18) 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 BALL ASSIGNMENT 58-Ball FBGA 1 A B C D E F G A11 2 A8 3 VSS 4 VCC 5 VPP 6 A18 7 A6 8 A4 A12 A9 A20 CLK RST# A17 A5 A3 A13 A10 ADV# WE# A19 A7 A2 A15 A14 WAIT# A16 DQ12 WP# A1 VCCQ DQ15 DQ6 DQ4 DQ2 DQ1 CE# A0 VSS DQ14 DQ13 DQ11 DQ10 DQ9 DQ0 OE# DQ7 VSSQ DQ5 VCC DQ3 VCCQ DQ8 VSSQ Top View (Ball Down) NOTE: See page 7 for Ball Description Table. See page 43 for mechanical drawing. OPTIONS * Timing 70ns access 80ns access * Frequency 54 MHz 40 MHz No burst operation * Boot Block Configuration Top Bottom * Package 58-ball FBGA (8 x 7 ball grid) * Operating Temperature Range Extended (-40C to +85C) Part Number Example: MARKING -70 -80 52 4 None T B FH ET MT28F322D20FH-804 BET 1 (c)2002, Micron Technology, Inc. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY GENERAL DESCRIPTION The MT28F322D20 and MT28F322D18 are highperformance, high-density, nonvolatile Flash memory solutions that can significantly improve system performance. This new architecture features a two-memorybank configuration that supports dual-bank operation with no latency. A high-performance bus interface allows a fast burst or page mode data transfer; a conventional asynchronous bus interface is provided as well. The devices allow soft protection for blocks, as readonly, by configuring soft protection registers with dedicated command sequences. For security purposes, two 64-bit chip protection registers are provided. The embedded WORD WRITE and BLOCK ERASE functions are fully automated by an on-chip write state machine (WSM). Two on-chip status registers, one for each of the two memory partitions, can be used to monitor the WSM status and to determine the progress of the program/erase task. The erase/program suspend functionality allows compatibility with existing EEPROM emulation software packages. The devices are manufactured using 0.18m process technology. Please refer to the Micron Web site (www.micron.com/ flash) for the latest data sheet. ARCHITECTURE AND MEMORY ORGANIZATION The Flash devices contain two separate banks of memory (bank a and bank b) for simultaneous READ and WRITE operations and are available in the following bank segmentation configuration: * Bank a is one-fourth of the memory containing 8 x 4K-word parameter blocks, while the remainder of bank a is split into 15 x 32K-word blocks. * Bank b represents three-fourths of the memory, is equally sectored, and contains 48 x 32K-word blocks. Figures 2 and 3 show the bottom and top memory organizations. DEVICE MARKING Due to the size of the package, Micron's standard part number is not printed on the top of each device. Instead, an abbreviated device mark comprised of a five-digit alphanumeric code is used. The abbreviated device marks are cross referenced to the Micron part numbers in Table 1. Table 1 Cross Reference for Abbreviated Device Marks PART NUMBER MT28F322D20FH-705 TET MT28F322D20FH-705 BET MT28F322D20FH-804 TET MT28F322D20FH-804 BET MT28F322D18FH-705 TET MT28F322D18FH-705 BET MT28F322D18FH-804 TET MT28F322D18FH-804 BET PRODUCT MARKING FW546 FW547 FW548 FW549 FW558 FW559 FW543 FW542 SAMPLE MARKING FX546 FX547 FX548 FX549 FX558 FX559 FX543 FX542 MECHANICAL SAMPLE MARKING FY546 FY547 FY548 FY549 FY558 FY559 FY543 FY542 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY PART NUMBERING INFORMATION Micron's low-power devices are available with several different combinations of features (see Figure 1). Valid combinations of features and their corresponding part numbers are listed in Table 2. Figure 1 Part Number Chart MT 28F 322 D20 FH-80 4 B ET Micron Technology Flash Family 28F = Dual-Supply Flash Operating Temperature Range ET = Extended (-40C to +85C) Boot Block Starting Address B = Bottom boot T = Top boot Density/Organization/Banks 322 = 32Mb (2,048K x 16) bank a = 1/4; bank b = 3/4 Burst Mode Frequency Blank = None 4 = 40 MHz 5 = 54 MHz (MT28F322D20) or 52 MHz (MT28F322D18) Read Mode Operation D = Asynchronous/Page/Burst Read Operating Voltage Range 18 = 1.70V-1.90V 20 = 1.80V-2.20V VCC 20 = 1.80V-2.25V VCCQ Access Time -70 = 70ns -80 = 80ns Package Code FH = 58-ball FBGA (8 x 7 grid) Table 2 Valid Part Number Combinations ACCESS TIME (ns) 70 70 80 80 70 70 80 80 BOOT BLOCK STARTING ADDRESS Bottom Top Bottom Top Bottom Top Bottom Top BURST FREQUENCY (MHz) 54 54 40 40 52 52 40 40 OPERATING TEMPERATURE RANGE -40oC to +85oC -40oC to +85oC -40oC to +85oC -40oC to +85oC -40oC to +85oC -40oC to +85oC -40oC to +85oC -40oC to +85oC PART NUMBER MT28F322D20FH-705 BET MT28F322D20FH-705 TET MT28F322D20FH-804 BET MT28F322D20FH-804 TET MT28F322D18FH-705 BET MT28F322D18FH-705 TET MT28F322D18FH-804 BET MT28F322D18FH-804 TET 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY FUNCTIONAL BLOCK DIAGRAM PR Lock PR Lock Query Query/OTP OTP DQ0-DQ15 X DEC Data Input Buffer Data Register RST# CE# WE# OE# Y/Z DEC Bank 1 Blocks Y/Z Gating/Sensing Manufacturer's ID Device ID Block Lock RCR ID Reg. CSM Status Reg. WSM Program/ Erase Pump Voltage Generators Output Multiplexer DQ0-DQ15 I/O Logic Output Buffer A0-A20 Address Input Buffer Address CNT WSM WAIT# Address Multiplexer Y/Z DEC X DEC Y/Z Gating/Sensing Bank 2 Blocks ADV# Address Latch CLK BSM 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Figure 2 Bottom Boot Block Device Block 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 Bank b = 24Mb Block Size (K-bytes/K-words) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Address Range (x16) 1F8000h-1FFFFFh 1F0000h-1F7FFFh 1E8000h-1EFFFFh 1E0000h-1E7FFFh 1D8000h-1DFFFFh 1D0000h-1D7FFFh 1C8000h-1CFFFFh 1C0000h-1C7FFFh 1B8000h-1BFFFFh 1B0000h-1B7FFFh 1A8000h-1AFFFFh 1A0000h-1A7FFFh 198000h-19FFFFh 190000h-197FFFh 188000h-18FFFFh 180000h-187FFFh 178000h-17FFFFh 170000h-177FFFh 168000h-16FFFFh 160000h-167FFFh 158000h-15FFFFh 150000h-157FFFh 148000h-14FFFFh 140000h-147FFFh 138000h-13FFFFh 130000h-137FFFh 128000h-12FFFFh 120000h-127FFFh 118000h-11FFFFh 110000h-117FFFh 108000h-10FFFFh 100000h-107FFFh 0F8000h-0FFFFFh 0F0000h-0F7FFFh 0E8000h-0EFFFFh 0E0000h-0E7FFFh 0D8000h-0DFFFFh 0D0000h-0D7FFFh 0C8000h-0CFFFFh 0C0000h-0C7FFFh 0B8000h-0BFFFFh 0B0000h-0B7FFFh 0A8000h-0AFFFFh 0A0000h-0A7FFFh 098000h-097FFFh 090000h-097FFFh 088000h-087FFFh 080000h-087FFFh Block 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bank a = 8Mb Block Size (K-bytes/K-words) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 Address Range (x16) 078000h-07FFFFh 070000h-077FFFh 068000h-067FFFh 060000h-067FFFh 058000h-05FFFFh 050000h-057FFFh 048000h-04FFFFh 040000h-047FFFh 038000h-03FFFFh 030000h-037FFFh 028000h-02FFFFh 020000h-027FFFh 018000h-01FFFFh 010000h-017FFFh 008000h-00FFFFh 007000h-007FFFh 006000h-006FFFh 005000h-005FFFh 004000h-004FFFh 003000h-003FFFh 002000h-002FFFh 001000h-001FFFh 000000h-000FFFh 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Figure 3 Top Boot Block Device Block 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Bank a = 8Mb Block Size (K-bytes/K-words) 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Address Range (x16) 1FF000h-1FFFFFh 1FE000h-1FEFFFh 1FD000h-1FDFFFh 1FC000h-1FCFFFh 1FB000h-1FBFFFh 1FA000h-1FAFFFh 1F9000h-1F9FFFh 1F8000h-1F8FFFh 1F0000h-1F7FFFh 1E8000h-1EFFFFh 1E0000h-1E7FFFh 1D8000h-1DFFFFh 1D0000h-1D7FFFh 1C8000h-1CFFFFh 1C0000h-1C7FFFh 1B8000h-1BFFFFh 1B0000h-1B7FFFh 1A8000h-1AFFFFh 1A0000h-1A7FFFh 198000h-19FFFFh 190000h-197FFFh 188000h-18FFFFh 180000h-187FFFh Block 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bank b = 24Mb Block Size (K-bytes/K-words) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Address Range (x16) 178000h-17FFFFh 170000h-177FFFh 168000h-16FFFFh 160000h-167FFFh 158000h-15FFFFh 150000h-157FFFh 148000h-14FFFFh 140000h-147FFFh 138000h-13FFFFh 130000h-137FFFh 128000h-12FFFFh 120000h-127FFFh 118000h-11FFFFh 110000h-117FFFh 108000h-10FFFFh 100000h-107FFFh 0F8000h-0FFFFFh 0F0000h-0F7FFFh 0E8000h-0EFFFFh 0E0000h-0E7FFFh 0D8000h-0DFFFFh 0D0000h-0D7FFFh 0C8000h-0CFFFFh 0C0000h-0C7FFFh 0B8000h-0BFFFFh 0B0000h-0B7FFFh 0A8000h-0AFFFFh 0A0000h-0A7FFFh 098000h-09FFFFh 090000h-097FFFh 088000h-08FFFFh 080000h-087FFFh 078000h-07FFFFh 070000h-077FFFh 068000h-06FFFFh 060000h-067FFFh 058000h-05FFFFh 050000h-057FFFh 048000h-04FFFFh 040000h-047FFFh 038000h-03FFFFh 030000h-037FFFh 028000h-02FFFFh 020000h-027FFFh 018000h-01FFFFh 010000h-017FFFh 008000h-00FFFFh 000000h-007FFFh 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY BALL DESCRIPTIONS 58-BALL FBGA NUMBERS E8, D8, C8, B8, A8, B7, A7, C7, A2, B2, C2, A1, B1, C1, D2, D1, D4, B6, A6, C6, B3 B4 SYMBOL A0-A20 TYPE Input DESCRIPTION Address Inputs: Inputs for the addresses during READ and WRITE operations. Addresses are internally latched during READ and WRITE cycles. CLK Input Clock: Synchronizes the Flash memory to the system operating frequency during synchronous burst mode READ operations. When configured for synchronous burst mode READs, address is latched on the first rising (or falling, depending upon the read configuration register setting) CLK edge when ADV# is active or upon a rising ADV# edge, whichever occurs first. CLK is ignored during asynchronous access READ and WRITE operations and during READ PAGE ACCESS operations.1 Address Valid: Indicates that a valid address is present on the address inputs. Addresses are latched on the rising edge of ADV# during READ and WRITE operations. ADV# may be tied active during asynchronous READ and WRITE operations.1 Program/Erase Enable: [0.9V-1.95V or 11.4V-12.6V] Operates as input at logic levels to control complete device protection. Provides factory programming compatibility when driven to 11.4V-12.6V. Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby power mode. Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is either a WRITE to the command state machine (CSM) or to the memory array. Reset: When RST# is a logic LOW, the device is in reset mode, which drives the outputs to High-Z and resets the write state machine. When RST# is at logic HIGH, the device is in standard operation. When RST# transitions from logic LOW to logic HIGH, the device resets all blocks to locked and defaults to the read array mode. Write Protect: Controls the lock down function of the flexible locking feature. Data Inputs/Outputs: Inputs array data on the second CE# and WE# cycle during PROGRAM command. Inputs commands to the command user interface when CE# and WE# are active. DQ0-DQ15 output data when CE# and OE# are active. Wait: Provides data valid feedback during continuous burst read access. The signal is gated by OE# and CE#. This signal is always kept at a valid logic level. C4 ADV# Input A5 VPP Input E7 F8 C5 CE# OE# WE# Input Input Input B5 RST# Input D6 WP# Input Input/ Output F7, E6, E5, G5, DQ0-DQ15 E4, G3, E3, G1, G7, F6, F5, F4, D5, F3, F2, E2 D3 WAIT# Output NOTE: 1. The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. The WAIT# signal can be ignored when operating in asynchronous or page mode, as it is always held at logic "1" or "0," depending on the RCR8 setting (see Table 8). (continued on next page) 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY BALL DESCRIPTIONS (continued) 58-BALL FBGA NUMBERS A4, G4 E1, G6 G2, G8 A3, F1 C3, D7 SYMBOL VCC VCCQ VSSQ VSS - TYPE Supply Supply Supply Supply - DESCRIPTION Device Power Supply: [1.70V-1.90V (MT28F322D18) or 1.80V-2.20V (MT28F322D20)] Supplies power for device operation. I/O Power Supply: [1.70V-1.90V (MT28F322D18) or 1.80V-2.25V (MT28F322D20)] Supplies power for input/output buffers. I/O Ground. Do not float any ground ball. Do not float any ground ball. Contact ball is not physically present. 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY COMMAND STATE MACHINE (CSM) Commands are issued to the command state machine (CSM) using standard microprocessor write timings. The CSM acts as an interface between external microprocessors and the internal write state machine (WSM). The available commands are listed in Table 3, their definitions are given in Table 4, and their descriptions in Table 5. Program and erase algorithms are automated by an on-chip WSM. (For more specific information about the CSM transition states, see Micron technical note TN-28-33, "Command State Machine Description and Command Definition." Once a valid PROGRAM/ERASE command is entered, the WSM executes the appropriate algorithm, which generates the necessary timing signals to control the device internally to accomplish the requested operation. A command is valid only if the exact sequence of WRITEs is completed. After the WSM completes its task, the WSM status bit (SR7) (see Table 7) is set to a logic HIGH level (1), allowing the CSM to respond to the full command set again. CE#, ADV#, and OE# must be at a logic LOW level (VIL), and WE# and RST# must be at logic HIGH (VIH). Table 6 illustrates the bus operations for all the modes: write, read, reset, standby, and output disable. When the device is powered up, internal reset circuitry initializes the chip to a read array mode of operation. Changing the mode of operation requires that a command code be entered into the CSM. For each one of the two memory partitions, an on-chip status register is available. These two registers allow the progress of the various operations that can take place on a memory bank to be monitored. One of the two status registers is interrogated by entering a READ STATUS REGISTER command onto the CSM (cycle 1), specifying an address within the memory partition boundary, and reading the register data on I/Os DQ0-DQ7 (cycle 2). Status register bits SR0SR7 correspond to DQ0-DQ7 (see Table 7). COMMAND DEFINITION Once a specific command code has been entered, the WSM executes an internal algorithm, generating the necessary timing signals to program, erase, and verify data. See Table 4 for the CSM command definitions and data for each of the bus cycles. OPERATIONS Device operations are selected by entering a standard JEDEC 8-bit command code with conventional microprocessor timings into an on-chip CSM through I/Os DQ0-DQ7. The number of bus cycles required to activate a command is typically one or two. The first operation is always a WRITE. Control signals CE#, ADV#, and WE# must be at a logic LOW level (VIL), and OE# and RST# must be at logic HIGH (VIH). The second operation, when needed, can be a WRITE or a READ depending upon the command. During a READ operation, control signals STATUS REGISTER The status register allows the user to determine whether the state of a PROGRAM/ERASE operation is pending or complete. The status register is monitored by toggling OE# and CE# and reading the resulting status code on I/Os DQ0-DQ7. The high-order I/Os (DQ8-DQ15) Table 3 Command State Machine Codes For Device Mode Selection COMMAND DQ0-DQ7 40h/10h 20h 50h 60h 60h 70h 90h 98h B0h C0h D0h FFh 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 CODE ON DEVICE MODE Program setup/alternate program setup Block erase setup Clear status register Protection configuration setup Set read configuration register Read status register Read protection configuration register Read query Program/erase suspend Protection register program/lock Program/erase resume - erase confirm Read array 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY are set to 00h internally, so only the low-order I/Os (DQ0-DQ7) need to be interpreted. Address lines select the status register pertinent to the selected memory partition. Register data is updated and latched on the falling edge of ADV# or rising (falling) CLK when ADV# is LOW during synchronous burst mode or on the falling edge of OE# or CE#, whichever occurs last. Latching the data prevents errors from occurring if the register input changes during a status register monitoring. The status register provides the internal state of the WSM to the external microprocessor. During periods when the WSM is active, the status register can be polled to determine the WSM status. Table 7 defines the status register bits. After monitoring the status register during a PROGRAM/ERASE operation, the data appearing on DQ0-DQ7 remains as status register data until a new command is issued to the CSM. To return the device to other modes of operation, a new command must be issued to the CSM. COMMAND STATE MACHINE OPERATIONS The CSM decodes instructions for read array, read protection configuration register, read query, read status register, clear status register, program, erase, erase suspend, erase resume, program suspend, program resume, lock block, unlock block and lock down block, chip protection program, and set read configuration register. The 8-bit command code is input to the device on DQ0-DQ7 (see Table 3 for CSM codes and Table 4 for command definitions). During a PROGRAM or ERASE cycle, the CSM informs the WSM that a PROGRAM or ERASE cycle has been requested. During a PROGRAM cycle, the WSM controls the program sequences and the CSM responds to a PROGRAM SUSPEND command only. Table 4 Command Definitions COMMAND READ ARRAY READ PROTECTION CONFIGURATION REGISTER READ STATUS REGISTER CLEAR STATUS REGISTER READ QUERY BLOCK ERASE SETUP PROGRAM SETUP/ALTERNATE PROGRAM SETUP PROGRAM/ERASE SUSPEND PROGRAM/ERASE RESUME - ERASE CONFIRM LOCK BLOCK UNLOCK BLOCK LOCK DOWN BLOCK PROTECTION REGISTER PROGRAM PROTECTION REGISTER LOCK SET READ CONFIGURATION REGISTER NOTE: 1. BA: IA: ID: LPA: PA: PD: QA: QD: RCD: SRD: WA: WD: X: FIRST BUS CYCLE OPERATION ADDRESS1 DATA WRITE WA FFh WRITE IA 90h WRITE BA 70h WRITE BA 50h WRITE QA 98h WRITE BA 20h WRITE WA 40h/10h WRITE BA B0h WRITE BA D0h WRITE BA 60h WRITE BA 60h WRITE BA 60h WRITE PA C0h WRITE LPA C0h WRITE RCD 60h SECOND BUS CYCLE OPERATION ADDRESS1 DATA1 READ READ READ WRITE WRITE IA X QA BA WA ID SRD QD D0h WD WRITE WRITE WRITE WRITE WRITE WRITE BA BA BA PA LPA RCD 01h D0h 2Fh PD FFFDh 03h Address within the block Identification code address Identification code data Lock protection register address Protection register address Data to be written at the location PA Query code address Query code data Data to be written in the read configuration register Data read from the status register Word address of memory location to be written, or read Data to be written at the location WA "Don't Care" 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Table 5 Command Descriptions CODE DEVICE MODE 10h 20h Alt. Program Setup Erase Setup BUS CYCLE First First DESCRIPTION Operates the same as PROGRAM SETUP command Prepares the CSM for the ERASE CONFIRM command. If the next command is not an ERASE CONFIRM command, the command will be ignored, and the bank will go to read status mode and wait for another command. A two-cycle command: The first cycle prepares for a PROGRAM operation, and the second cycle latches addresses and data and initiates the WSM to execute the program algorithm. The flash outputs status register data on the rising edge of ADV#, or on the rising clock edge when ADV# is LOW during synchronous burst mode, or on the falling edge of OE# or CE#, whichever occurs first. The WSM can set the block lock status (SR1), VPP status (SR3), program status (SR4), and erase status (SR5) bits in the status register to "1," but it cannot clear them to "0." Issuing this command clears those bits to "0." Prepares the CSM for changes to the block locking status. If the next command is not BLOCK UNLOCK, BLOCK LOCK or BLOCK LOCK DOWN the command will be ignored, and the device will go to read status mode. Puts the device into the set read configuration mode so that it will be possible to set the option bits related to burst read mode. This command places the device into a read status register mode. Reading the device will output the contents of the status register for the addressed bank. The device will automatically enter this mode for the addressed bank after a PROGRAM or ERASE operation has been initiated. Puts the device into the read protection configuration mode so that reading the device will output the manufacturer/device codes, block lock status, protection register, or protection register lock status. Puts the device into the read query mode so that reading the device will output common flash interface information. Issuing this command will suspend the currently executing PROGRAM/ ERASE operation. The status register will indicate when the operation has been successfully suspended by setting either the program suspend (SR2) or erase suspend (SR6), and the WSM status bit (SR7) to a "1" (ready). The WSM will continue to idle in the suspend state, regardless of the state of all input control signals except RST#, which will immediately shut down the WSM and the remainder of the chip if RST# is driven to VIL. Writes a specific code into the device protection register. Locks the device protection register; data can no longer be changed. 40h Program Setup First 50h Clear Status Register First 60h Protection Configuration Setup Set Read Configuration Register First First 70h Read Status Register First 90h Read Protection Configuration Read Query Program/Erase Suspend First 98h B0h First First C0h Program Device Protection Register Lock Device Protection Register First First (continued on next page) 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Table 5 Command Descriptions (continued) CODE DEVICE MODE D0h Erase Confirm BUS CYCLE Second DESCRIPTION If the previous command was an ERASE SETUP command, then the CSM will close the address and data latches, and it will begin erasing the block indicated on the address pins. During programming/erase, the device will respond only to the READ STATUS REGISTER, PROGRAM SUSPEND, or ERASE SUSPEND commands. It will output status register data on the rising edge of ADV#, or on the rising clock edge when ADV# is LOW during synchronous burst mode, or on the falling edge of OE# or CE#, whichever occurs last. If a PROGRAM or ERASE operation was previously suspended, this command will resume the operation. During read array mode, array data will be output on the data bus. If the previous command was PROTECTION CONFIGURATION SETUP, the CSM will latch the address and lock the block indicated on the address bus. If the previous command was SET READ CONFIGURATION REGISTER, the configuration bits presented on the address bus will be stored into the read configuration register. If the previous command was PROTECTION CONFIGURATION SETUP, the CSM will latch the address and lock down the block indicated on the address bus. If the previous command was PROTECTION CONFIGURATION SETUP, the CSM will latch the address and unlock the block indicated on the address bus. If the block had been previously set to lock down, this operation will have no effect. Unassigned command that should not be used. Program/Erase Resume FFh 01h Read Array Lock Block First First Second 03h Read Configuration Register Data Lock Down Second 2Fh Second D0h Unlock Block Second 00h Invalid/Reserved 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY During an ERASE cycle, the CSM responds to an ERASE SUSPEND command only. When the WSM has completed its task, the WSM status bit (SR7) is set to a logic HIGH level and the CSM responds to the full command set. The CSM stays in the current command state until the microprocessor issues another command. The WSM successfully initiates an ERASE or PROGRAM operation only when VPP is within its correct voltage range. ister, the protection register, and PR lock status. Two bus cycles are required for this operation: the chip identification data is read by entering the command code 90h on DQ0-DQ7 to the bank containing address 00h and the identification code address on the address lines. Control signals CE#, ADV#, and OE# must be at a logic LOW level (VIL), and WE# and RST# must be at a logic HIGH level (VIH) to read data from the protection configuration register. Data is available on DQ0-DQ15. After data is read from the protection configuration register, the READ ARRAY command, FFh, must be issued to the bank containing address 00h prior to issuing other commands. See Table 12 for further details. READ QUERY The read query mode outputs common flash interface (CFI) data when the device is read (see Table 16). Two bus cycles are required for this operation. It is possible to access the query by writing the read query command code 98h on DQ0-DQ7 to the bank containing address 0h. Control signals CE#, ADV#, and OE# must be at a logic LOW level (VIL) and WE# and RST# must be at a logic HIGH level (VIH) to read data from the query. The CFI data structure contains information such as block size, density, command set, and electrical specifications. To return to read array mode, write the read array command code FFh on DQ0-DQ7. READ STATUS REGISTER The status register is read by entering the command code 70h on DQ0-DQ7. Two bus cycles are required for this operation: one to enter the command code and a second to read the status register. The address for both cycles must be in the same partition. In a READ cycle, the address is latched on the rising edge of the ADV# signal. Register data is updated and latched on the falling edge of ADV# or rising (falling) CLK when ADV# is LOW during burst mode, or on the falling edge of OE# or CE#, whichever occurs last. CLEAR STATUS REGISTER The internal circuitry can set, but not clear, the block lock status bit (SR1), the VPP status bit (SR3), the program status bit (SR4), and the erase status bit (SR5) of the status register. The CLEAR STATUS REGISTER command (50h) allows the external microprocessor to clear these status bits and synchronize to the internal operations. When the status bits are cleared, the device returns to the read array mode. READ OPERATIONS The following READ operations are available: READ ARRAY, READ PROTECTION CONFIGURATION REGISTER, READ QUERY and READ STATUS REGISTER. READ ARRAY The array is read by entering the command code FFh on DQ0-DQ7. Control signals CE#, ADV#, and OE# must be at a logic LOW level (VIL) and WE# and RST# must be at a logic HIGH level (VIH) to read data from the array. Data is available on DQ0-DQ15. Any valid address within any of the blocks selects that address and allows data to be read from that address. Upon initial power-up or device reset, the device defaults to the read array mode. READ PROTECTION CONFIGURATION DATA The read protection configuration mode outputs five types of information: the manufacturer/device identifier, the block locking status, the read configuration reg- 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Table 6 Bus Operations MODE Read (array, status registers, device identification register, or query) Standby Output disable Reset Write RST# VIH CE# VIL ADV# VIL OE# VIL WE# VIH ADDRESS DQ0-DQ15 X DOUT VIH VIH VIL VIH VIH VIH X VIL X X X VIL X X X VIH X X X VIL X X X X High-Z High-Z High-Z DIN Table 7 Status Register Bit Definitions WSMS 7 ESS 6 ES 5 PS 4 VPPS 3 PSS 2 BLS 1 R 0 STATUS BIT # STATUS REGISTER BIT SR7 DESCRIPTION WRITE STATE MACHINE STATUS (WSMS) Check write state machine bit first to determine word 1 = Ready program or block erase completion, before checking program 0 = Busy or erase status bits. ERASE SUSPEND STATUS (ESS) 1 = BLOCK ERASE Suspended 0 = BLOCK ERASE in Progress/Completed ERASE STATUS (ES) 1 = Error in Block Erasure 0 = Successful BLOCK ERASE PROGRAM STATUS (PS) 1 = Error in PROGRAM 0 = Successful PROGRAM VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP = OK PROGRAM SUSPEND STATUS (PSS) 1 = PROGRAM Suspended 0 = PROGRAM in Progress/Completed BLOCK LOCK STATUS (BLS) 1 = PROGRAM/ERASE Attempted on a Locked Block; Operation Aborted 0 = No Operation to Locked Blocks When ERASE SUSPEND is issued, WSM halts execution and sets both WSMS and ESS bits to "1." ESS bit remains set to "1" until an ERASE RESUME command is issued. When this bit is set to "1," WSM has applied the maximum number of erase pulses to the block and is still unable to verify successful block erasure. When this bit is set to "1," WSM has attempted but failed to program a word. The VPP status bit does not provide continuous indication of the VPP level. The WSM interrogates the VPP level only after the program or erase command sequences have been entered and informs the system if VPP < 0.9V. The VPP level is also checked before the PROGRAM/ERASE is verified by the WSM. When PROGRAM SUSPEND is issued, WSM halts execution and sets both WSMS and PSS bits to "1." PSS bit remains set to "1" until a PROGRAM RESUME command is issued. If a PROGRAM or ERASE operation is attempted to one of the locked blocks, this is set by the WSM. The operation specified is aborted and the device is returned to read status mode. SR6 SR5 SR4 SR3 SR2 SR1 SR0 RESERVED FOR FUTURE ENHANCEMENT This bit is reserved for future use. 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY PROGRAMMING OPERATIONS There are two CSM commands for programming: PROGRAM SETUP and ALTERNATE PROGRAM SETUP (see Table 3). After the desired command code is entered (10h or 40h command code on DQ0-DQ7), the WSM takes over and correctly sequences the device to complete the PROGRAM operation. Monitoring of the WRITE operation is possible through the status register (see the Status Register section). During this time, the CSM responds only to a PROGRAM SUSPEND command until the PROGRAM operation has been completed, after which all commands to the CSM become valid again. The PROGRAM operation can be suspended by issuing a PROGRAM SUSPEND command (B0h). Once the WSM has reached the suspend state, it allows the CSM to respond only to READ ARRAY, READ STATUS REGISTER, READ PROTECTION CONFIGURATION, READ QUERY, PROGRAM SETUP, or PROGRAM RESUME. During the PROGRAM SUSPEND operation, array data should be read from an address other than the one being programmed. To resume the PROGRAM operation, a PROGRAM RESUME command (D0h) must be issued to cause the CSM to clear the suspend state previously set (see Figure 4 for programming operation and Figure 5 for program suspend and program resume). Taking RST# to VIL during programming aborts the PROGRAM operation. During programming, VPP must remain in the appropriate VPP voltage range as shown in the recommended operating conditions table. Block erasure inside the memory array sets all bits within the address block to logic 1s. Erase is accomplished only by blocks; data at single address locations within the array cannot be erased individually. The block to be erased is selected by using any valid address within that block. Block erasure is initiated by a command sequence to the CSM: BLOCK ERASE SETUP (20h) followed by BLOCK ERASE CONFIRM (D0h) (see Figure 6). A twocommand erase sequence protects against accidental erasure of memory contents. When the BLOCK ERASE CONFIRM command is complete, the WSM automatically executes a sequence of events to complete the block erasure. During this sequence, the block is programmed with logic 0s, data is verified, all bits in the block are erased to logic 1 state, and finally verification is performed to ensure that all bits are correctly erased. The ERASE operation may be monitored through the status register (see the Status Register section). During the execution of an ERASE operation, the ERASE SUSPEND command (B0h) can be entered to direct the WSM to suspend the ERASE operation. Once the WSM has reached the suspend state, it allows the CSM to respond only to the READ ARRAY, READ STATUS REGISTER, READ QUERY, READ CHIP PROTECTION CONFIGURATION, PROGRAM SETUP, PROGRAM RESUME, ERASE RESUME and LOCK SETUP (see the Block Locking section). During the ERASE SUSPEND operation, array data must be read from a block other than the one being erased. To resume the ERASE operation, an ERASE RESUME command (D0h) must be issued to cause the CSM to clear the suspend state previously set (see Figure 7). It is also possible to suspend an ERASE in any bank and initiate a WRITE to another block in the same bank. After the completion of a WRITE, an ERASE can be resumed by writing an ERASE RESUME command. ERASE OPERATIONS An ERASE operation must be used to initialize all bits in an array block to "1s." After BLOCK ERASE CONFIRM is issued, the CSM responds only to an ERASE SUSPEND command until the WSM completes its task. 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Figure 4 Automated Word Programming Flowchart Start BUS OPERATION COMMAND WRITE WRITE PROGRAM SETUP WRITE DATA COMMENTS Data = 40h or 10h Addr = Address of word to be programmed Data = Word to be programmed Addr = Address of word to be programmed Status register data Toggle OE# or CE# to update status register. Check SR7 1 = Ready, 0 = Busy WRITE Issue PROGRAM SETUP Command and Word Address READ Issue Word Address and Word Data Standby Read Status Register Bits NO NO SR7 = 1? YES Full Status Register Check (optional)1 PROGRAM SUSPEND? PROGRAM SUSPEND Loop Repeat for subsequent words. Write FFh after the last word programming operation to reset the device to read array mode. YES Word Program Completed FULL STATUS REGISTER CHECK FLOW Read Status Register Bits BUS OPERATION COMMAND Standby Standby COMMENTS Check SR1 1 = Detect locked block Check SR32 1 = Detect VPP LOW Check SR43 1 = Word program error SR1 = 0? YES NO PROGRAM Attempted on a Locked Block Standby NO SR3 = 0? YES NO SR4 = 0? YES Word Program Passed VPP Range Error Word Program Failed NOTE: 1. Full status register check can be done after each word or after a sequence of words. 2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation attempts. 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Figure 5 PROGRAM SUSPEND/ PROGRAM RESUME Flowchart Start BUS OPERATION COMMAND WRITE READ PROGRAM SUSPEND COMMENTS Data = B0h Status register data Toggle OE# or CE# to update status register. Check SR7 1 = Ready Check SR2 1 = Suspended READ ARRAY Data = FFh Read data from block other than that being programmed PROGRAM RESUME Data = D0h Issue PROGRAM SUSPEND Command Standby Standby Read Status Register Bits WRITE READ WRITE NO SR7 = 1? YES NO SR2 = 1? YES Issue READ ARRAY Command PROGRAM Complete Finished Reading ? YES Issue PROGRAM RESUME Command NO PROGRAM Resumed 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Figure 6 BLOCK ERASE Flowchart Start Issue ERASE SETUP Command and Block Address BUS OPERATION COMMAND WRITE WRITE ERASE SETUP ERASE COMMENTS Data = 20h Block Addr = Address within block to be erased Data = D0h Block Addr = Address within block to be erased Status register data Toggle OE# or CE# to update status register. Check SR7 1 = Ready, 0 = Busy WRITE READ Issue BLOCK ERASE CONFIRM Command and Block Address Standby ERASE SUSPEND Loop NO NO Read Status Register Bits Repeat for subsequent blocks. Write FFh after the last BLOCK ERASE operation to reset the device to read array mode. SR 7 = 1? YES Full Status Register Check (optional)1 ERASE SUSPEND? YES BLOCK ERASE Completed FULL STATUS REGISTER CHECK FLOW Read Status Register Bits BUS OPERATION COMMAND Standby Standby Standby ERASE Attempted on a Locked Block COMMENTS Check SR1 1 = Detect locked block Check SR32 1 = Detect VPP block Check SR53 1 = BLOCK ERASE error NO SR1 = 0? YES NO SR3 = 0? YES NO SR5 = 0? YES BLOCK ERASE Passed VPP Range Error BLOCK ERASE Failed NOTE: 1. Full status register check can be done after each block or after a sequence of blocks. 2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full status is checked. 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Figure 7 ERASE SUSPEND/ERASE RESUME Flowchart Start BUS OPERATION COMMAND WRITE READ ERASE SUSPEND COMMENTS Data = B0h Status register data Toggle OE# or CE# to update status register. Check SR7 1 = Ready Check SR6 1 = Suspended Issue ERASE SUSPEND Command Standby Standby Read Status Register Bits WRITE READ READ ARRAY Data = FFh Read data from block other than that being erased. NO SR7 = 1? WRITE YES NO SR6 = 1? YES ERASE Complete PROGRAM ERASE RESUME Data = D0h READ or PROGRAM? READ Issue READ ARRAY Command PROGRAM Loop (Note 1) NO READ or PROGRAM Complete? YES Issue ERASE RESUME Command ERASE Continued2 NOTE: 1. See Word Programming Flowchart for complete programming procedure. 2. See BLOCK ERASE Flowchart for complete erasure procedure. 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY READ-WHILE-WRITE/ERASE CONCURRENCY It is possible for the device to read from one bank while erasing/writing to another bank. Once a bank enters the WRITE/ERASE operation, the other bank automatically enters read array mode. For example, during a READ CONCURRENCY operation, if a PROGRAM/ERASE command is issued in bank a, then bank a changes to the read status mode and bank b defaults to the read array mode. The device will read from bank b if the latched address resides in bank b (see Figure 8). Similarly, if a PROGRAM/ERASE command is issued in bank b, then bank b changes to read status mode and bank a defaults to read array mode. When returning to bank a, the device will read PROGRAM/ERASE status if the latched address resides in bank a. A correct bank address must be specified to read status register after returning from concurrent read in the other bank. When reading the CFI or the chip protection register, concurrent operation is not allowed on the top boot device. Concurrent READ of the CFI or the chip protection register is only allowed when a PROGRAM or ERASE operation is performed on bank b on the bottom boot device. For a bottom boot device, reading of the CFI table or the chip protection register is only allowed if bank b is in read array mode. For a top boot device, reading of the CFI table or the chip protection register is only allowed if bank a is in read array mode. provides the read mode (burst, synchronous, or asynchronous), burst order, latency counter, and burst length. After executing this command, the device returns to read array mode. READ CONFIGURATION The device supports three read configurations: asynchronous, synchronous burst mode, and page mode. The bit RCR15 (see Table 9) in the read configuration register sets the read configuration. Asynchronous random mode is the default read mode. At power-up, the RCR is set to BBCFh. Status registers and the device identification register support asynchronous and single synchronous READ operations only. Figure 8 READ-While-WRITE Concurrency Bank a 1 - Erasing/writing to bank a 2 - Erasing in bank a can be suspended, and a WRITE to another block in bank a can be initiated. 3 - After the WRITE in that block is complete, an ERASE can be resumed by writing an ERASE RESUME command. 1 - Reading bank a Bank b 1 - Reading from bank b READ CONFIGURATION REGISTER (RCR) MODE The SET READ CONFIGURATION REGISTER command is a WRITE operation to the read configuration register (RCR). It is a two-cycle command sequence. Read configuration setup is written, followed by a second write that specifies the data to be written to the read configuration register. The data is placed on the address bus A0-A15, and it is latched on the rising edge of ADV#, CE#, or WE#, whichever occurs first. The read configuration 1 - Erasing/writing to bank b 2 - Erasing in bank b can be suspended, and a WRITE to another block in bank b can be initiated. 3 - After the WRITE in that block is complete, an ERASE can be resumed by writing an ERASE RESUME command. 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Table 8 Read Configuration Register RM 15 BS 7 BIT # 15 14 13-11 R 14 CC 6 DESCRIPTION Read Mode (RM) Reserved Latency Counter (LC) LC2 13 R 5 LC1 12 R 4 FUNCTION 0 = Synchronous Burst Access Mode 1 = Asynchronous/Page Access Mode (Default) Default = 0 Sets the number of clock cycles before valid data out: 000 = Code 0 - reserved 001 = Code 1 - reserved 010 = Code 2 011 = Code 3 100 = Code 4 101 = Code 5 - reserved 110 = Code 6 - reserved 111 = Code 7 - reserved (Default) Default = 0 Sets the data output configuration: 0 = Hold data for one clock 1 = Hold data for two clocks (Default) Controls the behavior of the WAIT# output signal: 0 = WAIT# asserted during delay 1 = WAIT# asserted one data cycle before delay (Default) Specifies the order in which data is addressed in synchronous burst mode: 0 = Interleaved 1 = Linear (Default) Defines the clock edge on which the BURST operation starts and data is referenced: 0 = Falling edge 1 = Rising edge (Default) Default = 0 0 = Burst wraps within the burst length 1 = Burst no wrap (Default) Sets the number of words the device will output in burst mode: 001 = 4 words 010 = 8 words 111 = Continuous burst (Default) LC0 11 BW 3 R 10 BL2 2 HDO 9 BL1 1 WC 8 BL0 0 10 9 Reserved Hold Data Out (HDO) 8 Wait Configuration (WC) 7 Burst Sequence (BS) 6 Clock Configuration (CC) 5-4 3 2-0 Reserved Burst Wrap (BW) Burst Length (BL) 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY LATENCY COUNTER The latency counter provides the number of clocks that must elapse after ADV# is set active before data will be available. This value depends on the input clock frequency. See Table 9 for the specific input clock frequency configuration code. See Figure 9 also. Table 9 Clock Frequency vs. First Access Latency MAX LATENCY CLK CYCLES FREQUENCY PERIOD CONFIGURATION FOR FIRST (MHz) (ns) COUNTER DATA -705 20 50 2 3 30 33 3 4 1 54 18.5 4 5 -804 20 50 2 3 30 33 3 4 40 25 4 5 SYNC ACCESS TIME (ns) 150 132 92.5 150 132 125 NOTE: 1. Maximum frequency for the MT28F322D18FH-705 device is 52 MHz. Figure 9 Latency Counter CLK VIH VIL A0-A20 VIH VIL ADV# VIH VIL VOH DQ0-DQ15 VO L Code 3 VOH DQ0-DQ15 VO L Code 4 VOH DQ0-DQ15 VO L VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT Code 2 VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID ADDRESS UNDEFINED Figure 10 Hold Data Output Configuration CLK Hold Data 1 CLK Hold Data 2 CLK DQ0-DQ15 VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT Figure 11 Wired OR WAIT# Configuration Wired OR READY # WAIT# Burst CPU/ Wait State Logic Bus data DATA MT28F322D18 DQ0-DQ15 DQ0-DQ15 VALID OUTPUT VALID OUTPUT . . WAIT# MT28F322D18 DQ0-DQ15 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY HOLD DATA OUTPUT CONFIGURATION The hold data output configuration specifies for how many clocks data will be held valid. (See Figure 10.) WAIT# CONFIGURATION The wait configuration bit, RCR8, sets the behavior of the WAIT# output signal. The WAIT# signal can be active during an output delay or one data cycle before delay when continuous burst length is enabled. WAIT# = 1 indicates valid data when RCR8 = 0. WAIT# = 0 indicates invalid data when RCR8 = 0. The setting of wait before or wait during RCR8 will depend on the system and CPU characteristic. If RCR3 = 1 (no wrap mode), then WAIT# can also be enabled in a four- or eight-word burst if the no-wrap burst crosses the first eight-word boundary. A Flash controller (CPU) is able to use this output signal to drive banks of the devices. An internal 1M pull-up resistor holds WAIT# = 1 and allows wired OR'ing multiple bank configurations, as shown in Figure 11. BURST SEQUENCE The burst sequence specifies the address order of the data in synchronous burst mode. It can be programmed as either linear or interleaved burst order. Continuous burst length only supports linear burst order. See Table 10 for more details. Table 10 Sequence and Burst Length STARTING ADDRESS . (DEC) 0 1 2 3 4 5 6 7 ... 14 15 ... 0 1 2 3 4 5 6 7 ... 14 15 WRAP RCR3 0 0 0 0 0 0 0 0 ... 0 0 ... NO WRAP RCR3 4-WORD BURST LENGTH LINEAR 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 INTERLEAVED 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 8-WORD BURST LENGTH LINEAR 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 ... INTERLEAVED 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 ... CONTINUOUS BURST LINEAR 0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10-... 5-6-7-8-9-10-11-... 6-7-8-9-10-11-12-... 6-7-8-9-10-11-12-13-... ... 14-15-16-17-18-19-20-.. 15-16-17-18-19-20-21-.. ... 0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10-... 5-6-7-8-9-10-11... 6-7-8-9-10-11-12... 7-8-9-10-11-12-13... ... 14-15-16-17-18-19-20-... 15-16-17-18-19-20-21-... ... ... ... ... ... 1 1 1 1 1 1 1 1 ... 1 1 ... 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 ... NA NA NA NA ... ... ... ... ... 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-14 ... ... NA NA NA NA NA NA NA NA ... 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY CLOCK CONFIGURATION The clock configuration configures the starting burst cycle, output data, and WAIT# signal to be asserted on the rising or falling edge of the clock. BURST WRAP The burst wrap option, RCR3, signals if a four- or an eight-word linear burst access wraps within the burst length or whether it crosses the eight-word boundary. In wrap mode (RCR3 = 0) the four- or eight-word access will wrap within the four or eight words, respectively. In nowrap mode (RCR3 = 1), the device operates similarly to a continuous burst. For example, in a four-word burst, nowrap mode, the possible linear burst sequences that do not assert WAIT# are: 0-1-2-3 8-9-10-11 1-2-3-4 9-10-11-12 2-3-4-5 10-11-12-13 3-4-5-6 11-12-13-14 4-5-6-7 12-13-14-15 The worst-case delay is seen at the end of the eightword boundary: 7-8-9-10 and 15-16-17-18. In a fourword burst, wrap mode, no WAIT# is asserted, and the possible wrap sequences are: 0-1-2-3 5-6-7-4 1-2-3-0 6-7-4-5 2-3-0-1 7-4-5-6 3-0-1-2 8-9-10-11 4-5-6-7 9-10-11-8 etc. When the continuous burst option is selected, the internal address wraps to 000000h if the device is read past the last address. BURST LENGTH The burst length defines the number of words the device outputs. The device supports a burst length of four or eight words. The device can also be set in continuous burst mode. In this mode the device linearly outputs data until the internal burst counter reaches the end of the burstable address space. RCR2 sets the burst length. CONTINUOUS BURST LENGTH During continuous burst mode operation, the Flash memory may have an output delay when the burst sequence crosses the first eight-word boundary. Also, in four- or eight-word bursts with the burst wrap set to no wrap (RCR3 = 1), the Flash memory may have an output delay when the burst sequence crosses the first eightword boundary. The starting address dictates whether or not a delay occurs. If the starting address is aligned with an eight-word boundary, the delay is not seen. For a fourword burst, if the starting address is aligned with a fourword boundary, a delay is not seen. If the starting address is at the end of an eight-word boundary, the output delay is the maximum delay, equal to the latency counter setting. The delay happens only once during a continuous burst access. If the burst never crosses an eight-word boundary, the WAIT# is not asserted. The WAIT# informs the system if this output delay occurs. WAIT# SIGNAL IN BURST MODE In the continuous burst mode or in the four- or eightword burst mode with no wrap (RCR3 = 1), the output WAIT# informs the system when data is valid. When WAIT# is asserted during delay (RCR8 = 0), WAIT# = 1 indicates valid data, and WAIT# = 0 indicates invalid data. If RCR8 = 0, WAIT# is asserted on the same cycle on which the delay occurs. If RCR8 = 1, WAIT# is asserted one cycle before the delay occurs. BLOCK LOCKING The Flash devices provide a flexible locking scheme that allows each block to be individually locked or unlocked with no latency. The devices offer two-level protection for the blocks. The first level allows software-only control of block locking (for data, which needs to be changed frequently), while the second level requires hardware interaction before locking can be changed (code which does not require frequent updates). Control signals WP#, DQ1, and DQ0 define the state of a block; for example, state [001] means WP# = 0, DQ1 = 0 and DQ0 = 1. Table 11 defines all of the possible locking states. NOTE: All blocks are software-locked upon completion of a power-up sequence. LOCKED STATE After a power-up sequence completion, or after a reset sequence, all blocks are locked (states [001] or [101]). This means full protection from alteration. Any PROGRAM or ERASE operations attempted on a locked block will return an error on bit SR1 of the status register. The status of a locked block can be changed to unlocked or lock down using the appropriate software commands. Writing the lock command sequence, 60h followed by 01h, can lock an unlocked block. UNLOCKED STATE Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks return to the locked state when the device is reset or powered down. An unlocked block can be locked or locked down using the appropriate software command sequence, 60h followed by D0h (see Table 4). 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY LOCKED DOWN STATE Blocks that are locked down (state [011]) are protected from PROGRAM and ERASE operations, but their protection status cannot be changed using software commands alone. A locked or unlocked block can be locked down by writing the lock down command sequence, 60h followed by 2Fh. Locked down blocks revert to the locked state when the device is reset or powered down. The LOCK DOWN function is dependent on the WP# input. When WP# = 0, blocks in lock down [011] are protected from program, erase, and lock status changes. When WP# = 1, the lock down function is disabled ([111]), and locked down blocks can be individually unlocked by a software command to the [110] state, where they can be erased and programmed. These blocks can then be relocked [111] and unlocked [110] as desired while WP# remains HIGH. When WP# goes LOW, blocks that were previously locked down return to the locked down state [011] regardless of any changes made while WP# was HIGH. Device reset or power-down resets all locks, including those in lock down, to locked state (see Table 12). READING A BLOCK'S LOCK STATUS The lock status of every block can be read in the read device identification mode. To enter this mode, write 90h to the bank containing address 00h. Subsequent READs at block address +00002 will output the lock status of that block. The lowest two outputs, DQ0 and DQ1, represent the lock status. DQ0 indicates the block lock/unlock status and is set by the LOCK command and cleared by the UNLOCK command. It is also automatically set when entering lock down. DQ1 indicates lock down status and is set by the LOCK DOWN command. It can only be cleared by reset or power-down, not by software. Table 11 shows the locking state transition scheme. The READ ARRAY command, FFh, must be issued to the bank containing address 00h prior to issuing other commands. LOCKING OPERATIONS DURING ERASE SUSPEND Changes to block lock status can be performed during an ERASE SUSPEND by using the standard locking command sequences to unlock, lock, or lock down. This is useful in the case when another block needs to be updated while an ERASE operation is in progress. To change block locking during an ERASE operation, first write the ERASE SUSPEND command (B0h), then check the status register until it indicates that the ERASE operation has been suspended. Next, write the desired lock command sequence to block lock, and the lock status will be changed. After completing any desired LOCK, READ, or PROGRAM operations, resume the ERASE operation with the ERASE RESUME command (D0h). If a block is locked or locked down during an ERASE SUSPEND operation on the same block, the locking status bits will be changed immediately. Then, when the ERASE is resumed, the ERASE operation will complete. A locking operation cannot be performed during a PROGRAM SUSPEND. Table 11 Block Locking State Transition WP# 0 0 0 1 1 1 1 DQ1 0 0 1 0 0 1 1 DQ0 0 1 1 0 1 0 1 NAME Unlocked Locked (Default) Lock Down Unlocked Locked Lock Down Disabled Lock Down Disabled ERASE/PROG ALLOWED Yes No No Yes No Yes No LOCK To [001] No Change No Change To [101] No Change To [111] No Change UNLOCK No Change To [000] No Change No Change To [100] No Change To [110] LOCK DOWN To [011] To [011] No Change To [111] To [111] To [111] No Change 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY CHIP PROTECTION REGISTER A 128-bit chip protection register can be used to fulfill the security considerations in the system (preventing the device substitution). The 128-bit security area is divided into two 64-bit segments. The first 64 bits are programmed at the manufacturing site with a unique 64-bit unchangeable number. The other segment is left blank for customers to program as desired. (See Figure 12). READING THE CHIP PROTECTION REGISTER The chip protection register is read in the device identification mode. To enter this mode, load the 90h command to the bank containing address 00h. Once in this mode, READ cycles from addresses shown in Table 12 retrieve the specified information. To return to the read array mode, write the READ ARRAY command (FFh). The READ ARRAY command, FFh, must be issued to the bank containing address 00h prior to issuing other commands. PROGRAMMING THE CHIP PROTECTION REGISTER The first 64 bits (PR1) of the protection register (addresses 81h-84h) are programmed with a unique identifier at the factory. DQ0 of the PR lock register (address 80h) is programmed to a "0" state, locking the first 64 bits and preventing any further programming. The second 64 bits (PR2) is a user area (addresses 85h- 88h), where the user can program any information into this area as long as DQ1 of the PR lock register remains unprogrammed. After DQ1 of the PR lock register is programmed, no further programming is allowed on PR2. The programming sequence is similar to array programming except that the PROTECTION REGISTER PROGRAMMING SETUP command (C0h) is issued instead of an ARRAY PROGRAMMING SETUP command (40h), followed by the data to be programmed at addresses 85h- 88h. To program the PR lock bit for PR2 (to prevent further programming), use the above sequence on address 80h, with data of FFFDh (DQ1 = 0). Figure 12 Protection Register Memory Map 88h 85h 84h 4 Words User-Programmed 4 Words Factory-Programmed 81h 80h PR Lock 0 Table 12 Chip Configuration Addressing1 ITEM Manufacturer Code (x16) Device Code Top boot configuration Bottom boot configuration Block Lock Configuration Block is unlocked Block is locked Block is locked down ADDRESS2 00000h 00001h 44B4h 44B5h XX002h Lock DQ0 = 0 DQ0 = 1 DQ1 = 1 RCR PR Lock Factory Data User Data DATA 002Ch * * * * * Read Configuration Register Chip Protection Register Lock Chip Protection Register 1 Chip Protection Register 2 00005h 80h 81h-84h 85h-88h NOTE: 1. Other locations within the configuration address space are reserved by Micron for future use. 2. "XX" specifies the block address of lock configuration. 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY ASYNCHRONOUS READ MODE The asynchronous read mode is the default read configuration state. To use the device in an asynchronousonly application, ADV# and CLK must be tied to VSS and WAIT# should be floated. Toggling the address lines from A0 to A20, the access is purely random (tAA). The ADV# signal needs to be toggled to latch the address, the CE# signal needs to go LOW, and the OE# signal needs to go LOW. In this case the data is placed on the data bus and the processor is ready to receive the data. 2. If one bank is in program or erase mode and the application starts burst access in that bank, then the status register data is returned. The internal address counter is incremented at every clock pulse. 3. If burst is started in one bank and the bank boundary is crossed, and the other bank is in program or erase mode, then the status register data is returned as the first location of the bank. If the application keeps clocking, the internal address counter gets incremented at every clock cycle. If bank end is crossed, then data from the other bank is returned as shown in Figure 13. SYNCHRONOUS BURST READ MODE The burst read mode is used to achieve a faster data rate than is possible with asynchronous read mode. The rising edge of the clock CLK is used to latch the address with CE# and ADV# LOW (see timing diagram: Single Synchronous READ Operation). The burst read configuration is set in the read configuration register, where frequency, data output, WAIT# signal, burst sequence, clock, and burst length are configured setting the related bits. All blocks in both banks are burstable. The BURST READ works across the bank boundary in the following way: 1. In READ operation there is no bank boundary as far as burst access is concerned. If, for example, burst starts in bank a, the application can keep clocking until bank boundary is reached and then read from bank b. If the application keeps clocking beyond bank b last location, then the internal counter restarts from bank a first address. (See Figure 13.) Figure 13 Bank Boundary Wrapping (Bottom Boot Example) Bank a start address 0 00000h Bank a end address Bank b start address 0 7FFFFh 0 80000h Bank a bank boundary Bank b Bank b end address 1 FFFFFh 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY ASYNCHRONOUS PAGE READ MODE After power-up or reset, the device operates in page mode over the whole memory array. The page size can be customized at the factory to four or eight words as required; but if no specification is made, the normal size is eight words. The initial portion of the page mode cycle is the same as the asynchronous access cycle. Holding CE# LOW and toggling addresses A0-A2 allows random access of other words in the page. STANDBY MODE ICC supply current is reduced by applying a logic HIGH level on CE# and RST# to enter the standby mode. In the standby mode, the outputs are High-Z. Applying a CMOS logic HIGH level on CE# and RST# reduces the current to ICC4 (MAX). If the device is deselected during an ERASE operation or during programming, the device continues to draw current until the operation is complete. VPP/VCC PROGRAM AND ERASE VOLTAGES The Flash devices provide in-system programming and erase with VPP in the 0.9V-2.2V range (VPP1). The 12V VPP (VPP2) mode programming is offered for compatibility with existing programming equipment. The device can withstand 100,000 WRITE/ERASE operations when VPP = VPP1 or 100 WRITE/ERASE operations and 10 cumulative hours when VPP = VPP2. In addition to the flexible block locking, the VPP programming voltage can be held LOW for absolute hardware write protection of all blocks in the Flash device. When VPP is below VPPLK, any PROGRAM or ERASE operation will result in an error, prompting the corresponding status register bit (SR3) to be set. During WRITE and ERASE operations, the WSM monitors the VPP voltage level. WRITE/ERASE operations are allowed only when VPP is within the ranges specified in Table 13. When VCC is below VLKO or VPP is below VPPLK, any WRITE/ERASE operation will be prevented. AUTOMATIC POWER SAVE MODE (APS) Substantial power savings are realized during periods when the array is not being read and the device is in the active mode. During this time the device switches to the automatic power save mode. When the device switches to this mode, ICC is reduced to a level comparable to ICC4. Further power savings can be realized by applying a logic HIGH level to CE# to place the device in standby mode. The low level of power is maintained until another operation is initiated. In this mode, the I/Os retain the data from the last memory address read until a new address is read. This mode is entered automatically if no address or control signals toggle. DEVICE RESET To correctly reset the Flash devices, the RST# signal must be asserted (RST# = VIL) for a minimum of tRP. After reset, the devices can be accessed for a READ operation with a delayed access time of tRWH from the rising edge of RST#. The circuitry used for generating the RST# signal needs to be common with the rest of the system reset to ensure that correct system initialization occurs. Please refer to the timing diagram for further details. Table 13 VPP Range (V) MIN 0.9 11.4 MAX 2.25 12.6 POWER-UP SEQUENCE The following power-up sequence is recommended to properly initialize internal chip operations: * At power-up, RST# should be kept at VIL for 2s after VCC reaches VCC (MIN). * VCCQ should not come up before VCC. * VPP should be kept at VIL to maximize data integrity. When the power-up sequence is completed, RST# should be brought to VIH. To ensure a proper power-up, the rise time of RST (10%-90%) should be < 10s. In System (VPP1) In Factory (VPP2) 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY ABSOLUTE MAXIMUM RATINGS* Voltage to Any Ball Except VCC and VPP with Respect to VSS ........................ -0.5V to +2.45V VPP Voltage (for BLOCK ERASE and PROGRAM with Respect to VSS) .................... -0.5V to +13.5V** VCC and VCCQ Supply Voltage with Respect to VSS ........................ -0.3V to +2.45V Output Short Circuit Current ................................ 100mA Operating Temperature Range ................ -40oC to +85oC Storage Temperature Range .................. -55oC to +125oC Soldering Cycle ............................................. 260oC for 10s *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Maximum DC voltage on VPP may overshoot to +13.5V for periods < 20ns. RECOMMENDED OPERATING CONDITIONS PARAMETER Operating temperature VCC supply voltage (MT28F322D20) VCC supply voltage (MT28F322D18) I/O supply voltage (MT28F322D20) I/O supply voltage (MT28F322D18) VPP voltage VPP in-factory programming voltage Block erase cycling (VPP = VPP1) Block erase cycling (VPP = VPP2) NOTE: 1. VPP = VPP2 is a maximum of 10 cumulative hours. SYMBOL tA MIN -40 1.80 1.70 1.80 1.70 0.9 11.4 - - MAX +85 2.20 1.90 2.25 1.90 2.25 12.6 100,000 100 UNITS o NOTES C VCC VCC VCCQ VCCQ VPP1 VPP2 V V V V V V Cycles Cycles 1 Figure 14 AC Input/Output Reference Waveform VCC Input VSS VCC/2 Test Points VCCQ/2 Output AC test inputs are driven at VCC for a logic 1 and VSS for a logic 0. Input timing begins at VCC/2, and output timing ends at VCCQ/2. Input rise and fall times (10% to 90%) < 5ns. Figure 15 Output Load Circuit VCC 14.5K I/O 14.5K VSS 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 30pF 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY CAPACITANCE (TA = +25C; f = 1 MHz) PARAMETER/CONDITION Input Capacitance Output Capacitance SYMBOL C COUT TYP 7 9 MAX 12 12 UNITS pF pF DC CHARACTERISTICS1 PARAMETER Input Low Voltage Input High Voltage Output Low Voltage IOL = 100A Output High Voltage IOH = -100A VPP Lockout Voltage VPP During PROGRAM/ERASE Operations VCC Program/Erase Lock Voltage Input Leakage Current Output Leakage Current VCC Asynchronous Random Read, 70ns cycle VCC Page Mode Read Current, 70ns/30ns cycle VCC Burst Mode Read Current , 18.5ns cycle VCC Standby Current VCC Program Current VCC Erase Current VCC Erase Suspend Current VCC Program Suspend Current Read-While-Write Current VPP Current (Read, Standby, Erase Suspend, Program Suspend) VPP VCC VPP VCC NOTE: 1. 2. 3. 4. 5. SYMBOL VIL VIH VOL VOH VPPLK VPP1 VPP2 VLKO IL IOZ ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICC8 ICC9 IPP1 MIN 0 VCCQ - 0.4V - VCCQ - 0.1V - 0.9 11.4 1 - - - - - - - - - - - MAX 0.4 VCCQ 0.10 - 0.4 2.2 12.6 - 1 1 15 5 10 50 55 65 50 50 80 UNITS V V V V V V V V A A mA mA mA A mA mA A A mA NOTES 2 2 3, 4 3, 4 4 5 5 - - 1 200 A A All currents are in RMS unless otherwise noted. VIL may decrease to -0.4V and VIH may increase to VCCQ + 0.3V for durations not to exceed 20ns. APS mode reduces ICC to approximately ICC4 levels. Test conditions: Vcc = VCC (MAX), CE# = VIL, OE# = VIH. All other inputs = VIH or VIL. ICC7 and ICC8 values are valid when the device is deselected. Any READ operation performed while in suspend mode will have an additional current draw of suspend current (ICC7 or ICC8). 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY ASYNCHRONOUS READ CYCLE TIMING REQUIREMENTS1 MT28F322D20 (VCC = 1.80V-2.25V) and MT28F322D18 (VCC = 1.70V-1.90V) -70 PARAMETER Address setup to ADV# HIGH CE# LOW to ADV# HIGH READ cycle time Address to output delay CE# LOW to output delay ADV# LOW to output delay ADV# pulse width LOW ADV# pulse width HIGH Address hold from ADV# HIGH Page address access OE# LOW to output delay RST# HIGH to output delay CE# or OE# HIGH to output High-Z Output hold from address, CE# or OE# change SYMBOL tAVS tCVS tRC tAA tACE tAADV tVP tVPH tAVH tAPA tAOE tRWH tOD tOH MIN 10 10 MAX MIN 10 10 -80 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns 70 70 70 70 10 10 3 30 25 200 15 0 0 10 10 3 80 80 80 80 30 30 200 25 NOTE: 1. See Figures 15 and 16 for timing requirements and load configuration. 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY BURST READ CYCLE TIMING REQUIREMENTS1 (MT28F322D20) -705 PARAMETER CLK period CLK HIGH (LOW) time CLK fall (rise) time Address valid setup to CLK ADV# LOW setup to CLK CE# LOW setup to CLK CLK to output delay Output hold from CLK Address hold from CLK CLK to WAIT# delay CE# HIGH between subsequent synchronous READs SYMBOL tCLK tKP tKHKL tAKS tVKS tCKS tACLK tKOH tAKH tKHTL tCBPH MIN 18.5 5 7 7 9 15 3.5 10 15 20 20 5 10 20 MAX MIN 25 7.5 7 7 13 20 -804 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns 3 5 BURST READ CYCLE TIMING REQUIREMENTS1 (MT28F322D18) -705 PARAMETER CLK period CLK HIGH (LOW) time CLK fall (rise) time Address valid setup to CLK ADV# LOW setup to CLK CE# LOW setup to CLK CLK to output delay Output hold from CLK Address hold from CLK CLK to WAIT# delay CE# HIGH between subsequent synchronous READs SYMBOL tCLK tKP tKHKL tAKS tVKS tCKS tACLK tKOH tAKH tKHTL tCBPH MIN 19.2 5 7 7 9 17 3.5 10 15 20 20 5 10 20 MAX MIN 25 7.5 7 7 13 20 -804 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns 3 5 NOTE: 1. See Figures 15 and 16 for timing requirements and load configuration. 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY WRITE CYCLE TIMING REQUIREMENTS -70/-80 PARAMETER HIGH recovery to WE# going LOW CE# setup to WE# going LOW Write pulse width ADV# pulse width Data setup to WE# going HIGH Address setup to WE# going HIGH ADV# setup to WE# going HIGH Address setup to ADV# going HIGH CE# hold from WE# HIGH Data hold from WE# HIGH Address hold from WE# HIGH Address hold from ADV# going HIGH Write pulse width HIGH RST# pulse width WP# setup to WE# going HIGH VPP setup to WE# going HIGH Write recovery before READ WP# hold from valid SRD VPP hold from valid SRD WE# HIGH to data valid SYMBOL tRS tCS tWP tVP tDS tAS tVS tAVS tCH tDH tAH tAVH tWPH tRP tRHS tVPS tWOS tRHH tVPPH tWB MIN 150 0 50 10 50 50 50 10 0 0 1.5 3 30 100 0 200 50 0 0 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tAA + 50 ERASE AND PROGRAM TIMING REQUIREMENTS -70/-80 PARAMETER 4KW block program time 32KW block program time Word program time 4KW block erase time 32KW block erase time Program suspend latency Erase suspend latency Chip programming time (APA) TYP 40 320 8 0.3 0.5 5 5 MAX 800 6,400 10,000 6 6 10 20 20 UNITS ms ms s s s s s s 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY SINGLE ASYNCHRONOUS READ OPERATION A0-A20 VIH VALID ADDRESS VIL tAA tRC tOD VIH ADV# VIL VIH CE# VIL tACE VIH OE# VIL tOH VIH WE# VIL VOH WAIT# VOL VOH DQ0-DQ15 VOL tAOE High-Z tRWH VALID OUTPUT RST# VIH VIL UNDEFINED READ TIMING PARAMETERS MT28F322D20 (VCC = 1.80V-2.25V) MT28F322D18 (VCC = 1.70V-1.90V) -70 SYMBOL tAA tACE tAOE tRC -80 MAX 70 70 25 70 MIN MAX 80 80 30 80 UNITS ns ns ns ns SYMBOL tRWH tOD tOH -70 MIN MAX 200 15 MIN -80 MAX 200 25 UNITS ns ns ns MIN 0 0 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY ASYNCHRONOUS PAGE MODE READ OPERATION VIH VALID ADDRESS VIL tRC A3-A20 A0-A2 VIH VALID ADDRESS VIL tAA VALID ADDRESS VALID ADDRESS VALID ADDRESS VIH ADV# VIL tOD VIH CE# VIL tACE VIH OE# VIL VIH WE# VIL VOH VOL tAOE tAPA tOH WAIT# VOH DQ0-DQ15 VOL High-Z tRWH VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VIH RST# VIL UNDEFINED READ TIMING PARAMETERS MT28F322D20 (VCC = 1.80V-2.25V) MT28F322D18 (VCC = 1.70V-1.90V) -70 SYMBOL tAA tACE tAPA tAOE -80 MAX 70 70 30 25 MIN MAX 80 80 30 30 UNITS ns ns ns ns SYMBOL tRC tRWH tOD tOH -70 MIN MAX 70 200 15 MIN -80 MAX 80 200 25 UNITS ns ns ns ns MIN 0 0 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY SINGLE SYNCHRONOUS READ OPERATION CLK VIH VIL tAKS tAKH A0-A20 VIH VIL VALID ADDRESS tAA tAVH ADV# VIH VIL tVPH tAADV tVP tVKS tOD CE# VIH VIL tACE tCVS tCKS OE# VIH VIL WE# VIH VIL WAIT# VOH VOL VOH VO L tACLK tAOE tKOH tOH DQ0-DQ15 High-Z VALID OUTPUT UNDEFINED READ TIMING PARAMETERS MT28F322D20 (VCC = 1.80V-2.25V) -705 SYMBOL tAKS tVKS tCKS tACLK tKOH tAKH tCVS tAA tACE tAADV tVP tVPH tAVH tAOE tOD tOH READ TIMING PARAMETERS MT28F322D18 (VCC = 1.70V-1.90V) -804 -705 MAX UNITS ns ns ns ns ns ns ns 80 80 80 10 10 3 ns ns ns ns ns ns ns ns ns SYMBOL tAKS tVKS tCKS tACLK tKOH tAKH tCVS tAA tACE tAADV tVP tVPH tAVH tAOE tOD tOH -804 MAX MIN 7 7 13 17 20 5 10 10 70 70 70 80 80 80 10 10 3 25 15 30 25 0 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MIN 7 7 9 MAX MIN 7 7 13 MIN 7 7 9 3 10 10 15 3 10 10 70 70 70 10 10 3 25 15 0 0 5 10 10 20 10 10 3 30 25 0 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY 4-WORD SYNCHRONOUS BURST OPERATION CLK VIH VIL tAKS tAKH A0-A20 VIH VIL VALID ADDRESS tAA tAVH ADV# VIH VIL tVPH tAADV tVP tVKS tOD CE# VIH VIL tACE tCVS tCKS OE# VIH VIL WE# VIH VIL WAIT# VOH VOL tAOE tKOH tOH DQ0-DQ15 VOH VO L High-Z tACLK VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT UNDEFINED READ TIMING PARAMETERS MT28F322D20 (VCC = 1.80V-2.25V) -705 SYMBOL tAKS tVKS tCKS tACLK tKOH tAKH tCVS tAA tACE tAADV tVP tVPH tAVH tAOE tOD tOH READ TIMING PARAMETERS MT28F322D18 (VCC = 1.70V-1.90V) -804 -705 MAX UNITS ns ns 20 5 10 10 ns ns ns ns ns 80 80 80 10 10 3 ns ns ns ns ns 30 25 0 ns ns ns ns SYMBOL tAKS tVKS tCKS tACLK tKOH tAKH tCVS tAA tACE tAADV tVP tVPH tAVH tAOE tOD tOH -804 MAX MIN 7 7 13 17 20 5 10 10 70 70 70 80 80 80 10 10 3 25 15 30 25 0 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MIN 7 7 9 MAX MIN 7 7 13 MIN 7 7 9 3 10 10 15 3 10 10 70 70 70 10 10 3 25 15 0 10 10 3 0 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 37 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY CONTINUOUS BURST READ SHOWING AN OUTPUT DELAY WITH RCR8 = 0(1) VIH VIL tCLK tKP tKHKL CLK A0-A20 VIH VIL ADV# VIH VIL CE# VIH VIL OE# VIH VIL WE# VIH VIL tKHTL tKHTL WAIT# VOH VOL VOH VO L DQ0-DQ15 VALID OUTPUT VALID OUTPUT INVALID OUTPUT VALID OUTPUT VALID OUTPUT tACLK tKOH UNDEFINED READ TIMING PARAMETERS MT28F322D20 (VCC = 1.80V-2.25V) -705 SYMBOL tCLK tKP tKHKL tACLK tKOH tKHTL READ TIMING PARAMETERS MT28F322D18 (VCC = 1.70V-1.90V) -804 -705 MAX UNITS ns ns ns ns ns ns SYMBOL tCLK tKP tKHKL tACLK tKOH tKHTL -804 MAX MIN 25 7.5 3 17 5 20 5 15 20 MAX UNITS ns ns ns ns ns ns MIN 18.5 5 MAX MIN 25 7.5 MIN 19.2 5 3 15 3.5 15 5 5 20 20 3.5 NOTE: 1. tCLK = 19.2ns (MIN) for the MT28F322D18 device. 2. tACLK = 17ns (MAX) for the MT28F322D18 device. 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 38 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY TWO-CYCLE PROGRAMMING/ERASE OPERATION A0-A20 VIH VIL VALID ADDRESS tAVS tVPH tAVH VALID ADDRESS tAS tAH VALID ADDRESS VIH ADV# VIL tVP tVS VIH CE# VIL tCS tCH tWPH tWP tWOS VIH OE# VIL VIH WE# VIL VIH DQ0-DQ15 VIL High-Z tRS tCH CMD tWB CMD/ DATA CMD/ DATA tDS STATUS VIH RST# VIL VIH WP# VIL tRHS tRHH tVPS tVPPH VIPPH VIPPLK VPP V IL UNDEFINED WRITE TIMING PARAMETERS -70/-80 SYMBOL tRS tCS tWP tVP tDS tAS tVS tAVS tCH tDH -70/-80 MAX UNITS ns ns ns ns ns ns ns ns ns ns SYMBOL tAH tAVH tWPH tVPH tRHS tVPS tWOS tRHH tVPPH tWB MIN 150 0 70 10 70 70 70 10 0 0 MIN 1.5 3 30 10 0 200 50 0 0 MAX UNITS ns ns ns ns ns ns ns ns ns tAA + 50 ns 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 39 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY RESET OPERATION VIH VIL RST# VIH VIL tRP CE# OE# VIH VIL DQ0-DQ15 VOH VOL tRWH READ AND WRITE TIMING PARAMETERS -70/-80 1.80V-2.25V MIN MAX 200 100 -70/-80 1.70V-1.90V MIN MAX 200 100 SYMBOL tRWH tRP UNITS ns ns 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 40 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Table 15 CFI OFFSET 00 01 02 - 0F 10, 11 12 13, 14 15, 16 17, 18 19, 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A, 2B 2C 2D, 2E 2F, 30 31, 32 33, 34 35, 36 DATA 2Ch B4h B5h reserved 0051, 0052 0059 0003, 0000 0039, 0000 0000, 0000 0000, 0000 0017 0022 00B4 00C6 0003 0000 0009 0000 000C 0000 0003 0000 0016 0001 0000 0000, 0000 0003 002F, 0000 0007, 0000 0000, 0001 0020, 0000 000E, 0000 000E, 0000 0000, 0001 0007, 0000 002F, 0000 Manufacturer code Top boot block device code Bottom boot block device code Reserved "QR" "Y" Primary OEM command set Address for primary extended table Alternate OEM command set Address for OEM extended table VCC MIN for Erase/Write; Bit7-Bit4 Volts in BCD; Bit3-Bit0 100mV in BCD VCC MAX for Erase/Write; Bit7-Bit4 Volts in BCD; Bit3-Bit0 100mV in BCD VPP MIN for Erase/Write; Bit7-Bit4 Volts in Hex; Bit3-Bit0 100mV in BCD VPP MAX for Erase/Write; Bit7-Bit4 Volts in Hex; Bit3-Bit0 100mV in BCD Typical timeout for single byte/word program, 2n s, 0000 = not supported Typical timeout for maximum size multiple byte/word program, 2n s, 0000 = not supported Typical timeout for individual block erase, 2n ms, 0000 = not supported Typical timeout for full chip erase, 2n ms, 0000 = not supported Maximum timeout for single byte/word program, 2n s, 0000 = not supported Maximum timeout for maximum size multiple byte/word program, 2n s, 0000 = not supported Maximum timeout for individual block erase, 2n ms, 0000 = not supported Maximum timeout for full chip erase, 2n ms, 0000 = not supported Device size, 2n bytes Bus Interface x16 = 1 Flash device interface description 0000 = async Maximum number of bytes in multi-byte program or page, 2n Number of erase block regions within device (4K words and 32K words) Top boot block device erase block region information 1, 8 blocks ... Bottom boot block device erase block region information 1, 8 blocks ... Top boot block device .....of 8KB Bottom boot block device .....of 8KB Top boot block 15 blocks of .... Bottom boot block 15 blocks of .... ......64KB Top boot block device .....48 blocks of Bottom boot block device .....48 blocks of (continued on next page) 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 DESCRIPTION 41 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Table 15 CFI (continued) OFFSET 37, 38 39, 3A 3B 3C 3D 3E 3F 40 41 DATA 0020, 0000 0000, 0001 0050, 0052 0049 0030 0031 00E6 0003 0000 0000 Top boot block device ......64KB Bottom boot block device ......64KB "PR" "I" Major version number, ASCII Minor version number, ASCII Optional Feature and Command Support Bit 0 Chip erase supported no = 0 Bit 1 Suspend erase supported = yes = 1 Bit 2 Suspend program supported = yes = 1 Bit 3 Chip lock/unlock supported = no = 0 Bit 4 Queued erase supported = no = 0 Bit 5 Instant individual block locking supported = yes = 1 Bit 6 Protection bits supported = yes = 1 Bit 7 Page mode read supported = yes = 1 Bit 8 Synchronous read supported = no = 0 Bit 9 Simultaneous operation supported = yes = 1 Program supported after erase suspend = yes Bit 0 block lock status active = yes; Bit 1 block lock down active = yes VCC supply optimum, 00 = not supported, Bit7-Bit4 Volts in BCD; Bit3-Bit0 100mV in BCD VPP supply optimum, 00 = not supported, Bit7-Bit4 Volts in BCD; Bit3-Bit0 100mV in BCD Number of protection register fields in JEDEC ID space Lock bytes LOW address, lock bytes HIGH address 2n factory programmed bytes, 2n user programmable bytes Background Operation 0000 = Not used 0001 = 4% block split 0002 = 12% block split 0003 = 25% block split 0004 = 50% block split Burst Mode Type 0000 = No burst mode 00x1 = 4 words MAX 00x2 = 8 words MAX 00x3 = 16 words MAX 001x = Linear burst, and/or 002x = Interleaved burst, and/or 004x = Continuous burst Page Mode Type 0000 = No page mode 0001 = 4-word page 0002 = 8-word page 0003 = 16-word page 0004 = 32-word page Not used DESCRIPTION 42 43, 44 45 46 47 48, 49 4A, 4B 4C 0001 0003, 0000 0018 00C0 0001 0080, 0000 0003, 0003 0003 4D 0072 4E 0002 4F 0000 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 42 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY 58-BALL FBGA 0.80 0.075 SEATING PLANE .10 C BALL A8 58X O 0.35 TYP SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS O 0.33 C SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or 62% Sn, 36% Pb, 2% Ag SOLDER BALL PAD: O .27mm 7.00 0.10 5.25 0.75 TYP BALL #1 ID SUBSTRATE: PLASTIC LAMINATE ENCAPSULATION MATERIAL: EPOXY NOVOLAC BALL A1 0.75 TYP 6.00 0.05 BALL #1 ID 12.00 .10 C L 2.25 0.05 4.50 1.50 (4X) C L 2.625 0.05 3.50 0.05 SUPPORT BALLS (4X) 1.20 MAX NOTE: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. DATA SHEET DESIGNATION No Mark: This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc. 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 43 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY REVISION HISTORY Rev. 4 .................................................................................................................................................................................... 7/02 * Removed PRELIMINARY DESIGNATION * Updated Status Register section * Updated command descriptions * Updated Read-While-Write/EraseConcurrency section * Updated timing diagrams * Changed interpage read access voltage from 1.70V to 1.80V * Changed intrapage read access voltage from 1.90V to 2.20V Rev. 3, PRELIMINARY ........................................................................................................................................................ 3/02 * Added Note 4 to DC Characteristics table Rev. 2, PRELIMINARY ........................................................................................................................................................ 1/02 * Added -70 and -80 speed grades for the MT28F322D18 * Removed -90 speed grade * Updated DC Characteristics Table * Updated CFI Table * Updated tAH and tRWH specifications * Changed data sheet from Advance to Preliminary Original document, Rev. 1, ADVANCE ............................................................................................................................ 7/01 2 Meg x 16 Async/Page/Burst Flash Memory MT28F322D20FH_4.p65 - Rev. 4, Pub. 7/02 44 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. |
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